Speaker
Description
DENEB is a 1024-channel mixed-signal ASIC under development at INFN in 110 nm CMOS technology for the readout of SiPM matrices across a wide temperature range (77–300 K). It is designed for GRAIN, a sub-detector of SAND at the Deep Underground Neutrino Experiment (DUNE) Near Detector facility (FNAL, USA). GRAIN is an active target consisting of a liquid-argon cryostat instrumented with cameras based on 32 × 32 SiPM arrays read out by the ASIC, enabling neutrino track reconstruction through scintillation light detection.
Each channel integrates a current conveyor, a transimpedance amplifier, two discriminators for double-threshold measurements, and four Time-to-Digital Converters (TDCs). The TDCs employ analog interpolation with Time-to-Analog Converters (TACs) and digitization via SAR or Wilkinson ADCs. The front end achieves Single-Photon Time Resolution (SPTR) below 100 ps, with time-walk correction using slew-rate or Time-over-Threshold (ToT) methods. A second branch enables charge measurement (photon counting) through a discrete-time current-to-frequency converter with real-time digitization. This provides a dynamic range exceeding 100 photoelectrons (PEs) and up to 50 simultaneous PEs, with sensitivity below 0.5 PE.
Each channel is implemented as a 500 μm-pitch square pixel. To mitigate TDC deadtime, four TDCs per pixel provide event derandomization, supporting event rates up to 10 MHz/pixel in ToT mode and about half in slew-rate mode. On-pixel logic buffers timing, charge, ToT, and ancillary data into two 64-bit event words, which are transferred via a daisy-chain bus to the end-of-column logic. Bandwidth can be doubled by disabling the second word and transmitting only timing data.
At the periphery, the end-of-column logic is equipped with SRAM capable of hosting up to 1024 (128-bit) or 2048 (64-bit) words per column, then transmits data through 32 SLVS/LVDS transceivers. Each operates at 320 Mbps (SDR) or 640 Mbps (DDR), yielding an aggregate bandwidth up to 32 × 640 Mbps using time-division multiplexing across parallel differential lines.
The chip occupies about 2 × 2.3 cm². A 44 × 36 grid of I/O pads on a 500 μm pitch covers the die. The 32 × 32 pixel matrix interfaces directly with the SiPM array through dedicated analog inputs, while supply and ground pads form a ring around the analog island to mitigate IR drop. At the bottom, 32 differential outputs serve the transceivers, supported by dedicated power pads.
Packaging development is ongoing with an external vendor, based on Fan-Out Wafer-Level Packaging (FOWLP). Cu-pillars grown on the pads connect to a silicon substrate that routes signals to a Ball Grid Array (BGA). The BGA maintains an identical pinout at a relaxed pitch for PCB compatibility. The package is optimized to minimize CTE mismatch, ensuring reliability from 300 K down to 77 K. A first engineering run and package production are scheduled for mid-2026. A second engineering run is planned for 2027.
At the conference, details on the ASIC floorplan, architecture, design trade-offs, key block features, and packaging technology challenges will be presented.
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