SVT - FE chip

Name: SVT - FE chip
Start: 2012-02-24T11:00:00+01:00
End: 2012-02-24T13:00:00+01:00
Location: No location set

Friday 24 Feb 2012, 11:00 → 13:00 Europe/Rome

Giuliana Rizzo (PI)

Description

EVO CONNECTION Title: SVT- FE chips Description: Community: SuperB Password: supersvt Meeting Access Information: - Meeting URL http://evo.caltech.edu/evoNext/koala.jnlp?meeting=M9MIMi2D2eD2D2929uDD99 - Password: supersvt - Phone Bridge ID: 481 8324 Password: 1229 Central European Time (+0100) Start 2012-02-24 11:00 End 2012-02-24 13:30 In case EVO doesn't work we will use the INFN Phone system: http://server10.infn.it/video/index.php?page=telephone_numbers - Dial code 3232 #

- 1
  
  Update on analog design for fast channels L0-L3
  
  Speaker: Lodovico Ratti (PV)
  
  Slides
- 2
  
  Update on analog design for L4-L5, Hit efficiency and time resolution
  
  Speaker: Dr Luca Bombelli (MI)
  
  Slides
- 3
  
  Update on in-strip logic design
  
  Speaker: Roberto Beccherle (GE)
  
  Slides
- 4
  
  Update on readout architecture VHDL simulation
  
  Speaker: Filippo Maria Giorgi (BO)
- 5
  
  Peripheral blocks
  
  Speaker: Valerio Re (PV)
- 6
  
  Discussion