SVT - FE chip

Friday 25 Nov 2011, 11:00 → 13:00 Europe/Rome

Giuliana Rizzo (PI)

EVO CONNECTION Title: SVT - FE chips Description: Community: SuperB Password: supersvt Meeting Access Information: - Meeting URL http://evo.caltech.edu/evoNext/koala.jnlp?meeting=M2MvMB2M2nDIDt999uDM92 - Password: supersvt - Phone Bridge ID: 436 0304 Password: 1229 Central European Time (+0100) Start 2011-11-25 11:00 End 2011-11-25 13:00 In case EVO doesn't work we will use the INFN Phone system: http://server10.infn.it/video/index.php?page=telephone_numbers - Dial code 3232 #

11:00 → 11:15 Update on analog design for fast channels L0-L3

Speaker: Lodovico Ratti (PV)

11:15 → 11:30 Update on analog design for L4-L5

Speaker: Carlo Ettore Fiorini (MI)

11:30 → 11:45 Update on in-strip logic design

Speaker: Roberto Beccherle (GE)

11:45 → 12:00 Update on readout architecture VHDL simulation

Speaker: Filippo Maria Giorgi (BO)

12:00 → 12:15 Peripheral blocks

Speaker: Valerio Re (PV)

12:15 → 13:00 Discussion