SVT - FE chip

Name: SVT - FE chip
Start: 2011-10-14T11:00:00+02:00
End: 2011-10-14T13:00:00+02:00
Location: No location set

Friday 14 Oct 2011, 11:00 → 13:00 Europe/Rome

Giuliana Rizzo (PI)

Description

EVO CONNECTION Title: SVT-FE chips Description: Community: SuperB Password: supersvt Meeting Access Information: - Meeting URL http://evo.caltech.edu/evoNext/koala.jnlp?meeting=MsMiMI2t2eD8Da9l9vDt9s - Password: supersvt - Phone Bridge ID: 415 5340 Password: 1229 Central European Summer Time (+0200) Start 2011-10-14 11:00 End 2011-10-14 13:00 In case EVO doesn't work we will use the INFN Phone system: http://server10.infn.it/video/index.php?page=telephone_numbers - Dial code 3232 #

- 11:00 → 11:15
  
  Update on analog design for fast channels L0-L3 15m
  
  Speaker: Lodovico Ratti (PV)
  
  Slides
- 11:15 → 11:30
  
  Update on analog design for L4-L5 15m
  
  Speaker: Carlo Ettore Fiorini (MI)
  
  Slides
- 11:30 → 11:45
  
  Update on in-strip logic design 15m
  
  Speaker: Roberto Beccherle (GE)
  
  Slides
- 11:45 → 12:00
  
  Update on readout architecture VHDL simulation 15m
  
  Speaker: Filippo Maria Giorgi (BO)
- 12:00 → 12:15
  
  Peripheral blocks 15m
  
  Speaker: Valerio Re (PV)
  
  Slides
- 12:15 → 13:00
  
  Discussion 45m