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draft talks for the review

→ Europe/Rome
Description
We put here our talks before Tuesday afternoon for everybody in Italy
    • 08:30 → 09:10
      Goal of the proposal: Motivations, requirements and technical specifications 40m
      Explain the physics and trigger motivations and how they translate into requirements and then into the technical specifications. Description of tradeoff analysis between costs, performance, complexity, which led to the proposed organization of the system and to the specific choice of technology.
      Speaker: Mel
      Slides
    • 09:10 → 09:30
      discussion 20m
      Speaker: everybody
    • 09:30 → 10:40
      Description of the system 1h 10m
      - hierarchy, - block diagrams including interfaces and signals - boards and ASIC functionalities - associative memory ASIC: functionality and block diagrams
      Speaker: Alberto Annovi
      Slides
    • 10:40 → 11:00
      Comparison with other technologies 20m
      - our ASIC solution compared to FPGAs, commercial CAMs, totally full custom ASIC - FTK versus CPU farm; probably deleted
      Speaker: paola
      Slides
    • 11:00 → 12:00
      discussion 1h
      Speaker: everybody
    • 12:00 → 13:30
      Lunch 1h 30m
    • 13:30 → 13:45
      Interface to TDAQ: FTK needs 15m
      - Spy Buffers for diagnostic and monitoring: from CDF to Atlas - Board Level diagnostic - Error recovering - Initialization: downloading patterns and constants - Monitoring tools
      Speaker: Francesco
      Slides
    • 13:45 → 13:55
      Integration in the TDAQ 10m
      Speaker: Jinlong
      Slides
    • 13:55 → 14:10
      Interface to L2 15m
      Speaker: Jinlong
      Slides
    • 14:10 → 14:20
      Interface to Inner Detector RODs 10m
      * Dual-port HOLA already covered so not part of this review. Flow control (XON/XOFF) was not part of the design then. We would like to understand what the status today and what engineering study has been done or will be done to implement it. * Specifically interface to the IBL ROD
      Speaker: Mel
      Slides
    • 14:20 → 14:40
      Interface to DCS - Infrastructures 20m
      DCS racks, rack location, crates, power, cooling
      Speaker: Agostino
      Slides
    • 14:40 → 15:00
      discussion 20m
      Speaker: everybody
    • 15:00 → 15:30
      Status of the R&D/project - Prototypes and results 30m
      New AMBoard New LAMB Clustering Mezzanine
      Speaker: Alberto Stabile
      Slides
    • 15:30 → 16:00
      Status of the R&D/project - Planning and status of System demonstrator 30m
      EDRO & Vertical slice Initial crate for consumption and cooling tests Small FTK on "barrel only" for 17,6 pile-up events
      Speaker: Marco
      Slides
    • 16:00 → 16:30
      Pending technical issues and plans to address and solve 30m
      High speed serial links and connections Density of chips in the AMboard Function density in AUXiliary boards AMChip density (number of patterns/mm^2) AMChip power consumption ROS/ROBIN configuration – bandwidth to Level-2
      Speaker: paola
      Slides
    • 16:30 → 16:45
      coffee break 15m
      Speaker: nessuno
    • 16:45 → 17:00
      Project definition and organization - milestones & work-plan 15m
      - Discussion of high level milestones - Deliverables, and work-plan
      Speaker: Paola
      Slides
    • 17:00 → 17:30
      Project definition and organization - costs, manpower evaluation, management 30m
      - Material cost estimates - Manpower estimates (FTEs, and type of FTEs) - Project organization: manpower and coordination Provisional organization and management until the upgrade project is approved.
      Speaker: Mel
      Slides
    • 17:30 → 17:50
      Details of FTK costs for Italy, USA, Japan, Germany 20m
      document