Chip logic overview - plans for the future - costs - schedule

• P. Giannetti

Changes to be implemented into our 2D chip. Variable resolution patterns ....

• A. Annovi

The 3D or 2,5D option

• P. Giannetti

Standard Cell design - tools - details {block diagrams, routing, critical lines...}

• F. Crescioli

Full custum design - tools - selective precharge - cell timing

• M. Beretta

Simulation - test vectors - chip tests

• I. Sacco

features necessary for LEVEL 1 apllication

• A. Shoening

DIscussion: questions and answers

• all

Funding agencies - other collaborators - EU applications...... - discussion

• P. Giannetti

free discussion

• all