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v3.2.9
-30 tiles have been produced with TiTiN backside and epoxy bonding have been shipped to Pisa
-will start building 30 tiles for MB classic this week, aim to finish this week. Will ship to Pisa early next week.
-awaiting 4th Au wafer from FBK to start building Au tiles
-work on setting up Auger valve, issues reported last week probably solved
Metallization:
-have built 7 tiles with Ag backside metallization
-first results reported on Ag tiles (from first 7 tiles produced). Comparison between Au and Ag backside looks similar for 6 of the 7 tiles. Testing the 7th to understand why it has higher R_d. May be a measurement issue.
-The 6 Ag tiles have room temp R_d in range of 38 Ohms, which is acceptable (cf Au 30 Ohms). At LN, the R_d is more similar between the two. Didn't expect a difference between Au and Ag, so this is a little surprising.
-gradually tuning Auger valve to decrease the solder over the 7 tiles, see similar results as solder reduced.
-spread of resistance at RT is small (with exception of 7th tile). At LN temp, the spread is a little larger than Au (again not expected), but still only few Ohms RMS.
-all immersed in LN and remain stable. And this is on FR4 substrates so should do better in Arlon.
-plan is to build a further 30 tiles with Ag backside for physics functionality measurements periodically in Pisa, and O(5) tile+ with Ag, monitored at LNGS, for aging.
Discussion:
-is it known which intermetallics will be formed with the new solder-metallization stack? This is eutectic solder (In-Sn, roughly 50:50), so here have In-Ag and Sn-Ag, no issues reported in literature for these.
-cross-section measured at STFC Interconnect of In-Au shows fractures in brittle intermetallic layer, John L to share image.
cathode-to-cathode resistance measurement to study bonding resistance.
-reported last week, saw larger than expected R_c-c, and clear difference between AlSi and AlCu, and increase of R_c-c over few days
-this week: studied if increasing the current had effect-- sweep in current and monitor of voltage shows that after a level the V remains constant with increasing on first sweep, and on second sweep get smaller R at I_max. Static R decreases as I_max increases. Indicates formation of some non-ohmic contact and can "break" it above 30 mA, to decrease bonding resistance from ~200 Ohms to ~20 Ohm level.
Thermal tests:
-acquired use of climatic chamber. Will store epoxy and solder tiles at constant temp (35-40 C) and humidity (80-90%) for 1 month to study effect on aging rate.
Discussion:
-suggest to try also with N2 bagged tile (to test effect of O2 on same 1 month time scale).
-comment: presence of halogens in flux can't be excluded, should investigate the solder composition carefully.
--Au-backside tiles have been soldered with this flux and smaller growth of R_d observed, so this argues against flux being cause of observed aging
--note: this effect not observed in FBK tiles
--AlSi significantly worse than AlCu with epoxy, so how can this be an effect of intermetallics since the epoxy only sees the TiTiN
Accordo Quadro extension not yet signed, expect will be some time.
-message: need the PO to construct the new reticules for DS20k
Discussion:
-DS needs to validate the final run with the final reticule with 25 wafers before can start full production, and need to receive these by first week of Sept. to stay on schedule.
-we have 3 remaining runs. Run 7 dedicated to final reticule. AR will confirm this week what to do with run 6.
Tile test stand:
-RHUL measured normal IV curve at RT after shipping
-acquisition software of I-V and waveforms working
-LN data acquired with different FBK SiPMs with x-ray line source, test full acquisition and control chain
-RHUL flange nearly complete, waiting for feedthrough to finish
-DS and GK sent gerber files for adapter boards, these have been ordered and will ship on Wed.
-laser fiber and adapters have arrived
-need power filter info from GK
vTile+:
-AR discussed with Genova, suggest QFN for smallest footprint for ASIC package. (JRM to check with KN)
-will make a vtile+ with wire bonded ASIC
-Davide design, send to UK in Aug. wk2, JRM to get it made and ship to Genova while LNGS off Aug. 15-30.
Boxes:
-modified mupi- Marco Carlini and Hanguo have drawings of mupi+ for tile+. Can use mupi+ to test everything with LED matrix and wirebonding etc.
-no design for cheaper thing yet, Manchester to investigate
Metal backside bonding:
-JRM to follow up indium corp quote-- can they reduce the flux? 10% for us would be fine.
-AR will send 1/4 wafer with Au, diced. IM to manage the shipping from UK, as before.
-Limited number of shippers (this is the box the wafer ring came in. JRM should buy some (or send them back). From Ultron, Iza has details. Estimate how many will we need during production operations, should look for boxes, not just single units.
QR code reader:
-laser engraved QR produced at RAL, 10 mm x 10 mm, can be read by Adriana's app.
-DS: space available on the tile is max 8 mm x 8 mm. RAL to test this space.
-DS to send the step file of the tile+
-Can UK engrave all the tiles for DS? JRM to confirm with JL.