PENDING:
1) Modello Verilog/VHDL single layer (assert/warning on timing issue).
2) Re-Do Floorplane (2.5V PADs, minimal changes discussed last week, include gds files provided by UMC). Resubmit to UMC for a check.
3) Include in the synthesys/simulation changes by Edoardo + Changes discussed last week for the precharge operation of the CAM.
4) Include JTAG blocks.
5) Note is out of sync !!!!!
6) LEF...
