Sep 10 – 12, 2014
University of Pisa
Europe/Rome timezone

Use of hardware accelerators for ATLAS computing

Sep 11, 2014, 6:30 PM
30m
University of Pisa

University of Pisa

<a target="_blank" href=https://www.google.com/maps/place/Dipartimento+di+Fisica/@43.720239,10.407985,17z/data=!3m1!4b1!4m2!3m1!1s0x12d591bb7d8c8ec9:0xbf91ddd442e32978>Polo Fibonacci</a> Largo Bruno Pontecorvo, 3 I-56127 Pisa <em>phone +39 050 2214 327</em>

Speakers

Mr Maik Dankel (CERN)Dr Sami Kama (Southern Methodist University Dallas/US)

Description

Modern HEP experiments produce tremendous amounts of data. These data are processed by in-house built software frameworks which have lifetimes longer than the detector itself. Such frameworks were traditionally based on serial code and relied on advances in CPU technologies, mainly clock frequency, to cope with increasing data volumes. With the advent of many-core architectures and GPGPUs this paradigm has to shift to parallel processing and has to include the use of co-processors. However, since the design of most existing frameworks is based on the assumption of frequency scaling and predate co-processors, parallelisation and integration of co-processors are not an easy task. The ATLAS experiment is an example of such a big experiment with a big software framework called Athena. In this talk we will present the studies on parallelisation and co-processor (GPGPU) use in data preparation and tracking for trigger and offline reconstruction as well as their integration into a multiple process based Athena framework.

Primary author

Dr Sami Kama (Southern Methodist University Dallas/US)

Presentation materials