Speaker
Stefano Gallorini
(PD)
Description
The LHCb experiment is entering in its upgrading phase, with its detector and read-out system re-designed to cope with the increased LHC energy after the long shutdown of 2018. In this upgrade, a trigger-less data acquisition is being developed to read-out the full detector at the bunch-crossing rate of 40 MHz. In particular, the High Level Trigger (HLT) system, where the bulk of the trigger decision is implemented via software on a CPU farm, has to be heavily revised.
Since the small LHCb event size (about 100 kB), many-core architectures such as General Purpose Graphics Processing Units (GPGPUs) and multi-core CPUs can be used to process many events in parallel for real-time selection, and may offer a solution for reducing the cost of the HLT farm. Track reconstruction and vertex finding are the more time-consuming applications running in HLT and therefore are the first to be ported on many-core.
In this talk we present our implementation of the existing tracking algorithms on GPGPU, discussing in detail the case of the VErtex LOcator detector (VELO), and we show the achieved performances. We discuss also other tracking algorithms that can be used in view of the LHCb upgrade.
Primary author
Stefano Gallorini
(PD)
Co-authors
Alessio Gianelle
(PD)
Mr
Alexey Badalov
(La Salle-URL, Spain)
Anna Lupato
(P)
Mr
Daniel Campora Perez
(CERN)
Donatella Lucchesi
(PD)
Dr
Gianmaria Collazuol
(PD)
Mr
Lorenzo Sestini
(INFN Padova)
Mr
Marco Corvo
(PD)
Mr
Niko Neufeld
(CERN)
Dr
Silvia Amerio
(PD)
Mr
Xavier Vilasis Cardona
(La Salle-URL, Spain)
