SVT - FE chip
Wednesday, 28 November 2012 -
15:00
Monday, 26 November 2012
Tuesday, 27 November 2012
Wednesday, 28 November 2012
15:00
Submission of a prototype chip with analog channels for L4-5
-
Bayan Nasri
(
MI
)
Submission of a prototype chip with analog channels for L4-5
Bayan Nasri
(
MI
)
15:00 - 15:15
15:15
Update on analog design for fast channels L0-L3 and peripheral blocks
-
Valerio Re
(
PV
)
Update on analog design for fast channels L0-L3 and peripheral blocks
Valerio Re
(
PV
)
15:15 - 15:30
15:30
Update on in-strip logic design
-
Roberto Beccherle
(
GE
)
Update on in-strip logic design
Roberto Beccherle
(
GE
)
15:30 - 15:45
15:45
Update on readout architecture VHDL simulation
-
Filippo Maria Giorgi
(
BO
)
Update on readout architecture VHDL simulation
Filippo Maria Giorgi
(
BO
)
15:45 - 16:00
16:00
Discussion
Discussion
16:00 - 17:00