SVT - FE chip
Friday 27 January 2012 -
11:00
Monday 23 January 2012
Tuesday 24 January 2012
Wednesday 25 January 2012
Thursday 26 January 2012
Friday 27 January 2012
11:00
Update on analog design for fast channels L0-L3
-
Lodovico Ratti
(
PV
)
Update on analog design for fast channels L0-L3
Lodovico Ratti
(
PV
)
11:00 - 11:15
11:15
Update on analog design for L4-L5
-
Carlo Ettore Fiorini
(
MI
)
Update on analog design for L4-L5
Carlo Ettore Fiorini
(
MI
)
11:15 - 11:30
11:30
Update on in-strip logic design
-
Roberto Beccherle
(
GE
)
Update on in-strip logic design
Roberto Beccherle
(
GE
)
11:30 - 11:45
11:45
Update on readout architecture VHDL simulation
-
Filippo Maria Giorgi
(
BO
)
Update on readout architecture VHDL simulation
Filippo Maria Giorgi
(
BO
)
11:45 - 12:00
12:00
Peripheral blocks
-
Valerio Re
(
PV
)
Peripheral blocks
Valerio Re
(
PV
)
12:00 - 12:15
12:15
Discussion
Discussion
12:15 - 13:00