Schedule AM_chip

given the fact that 

(1) TSMC 65 nm, low power, is now available as mini@sic (Vcc_core=1,2 V).

(2) 65 nm mini@sic is not much more expensive than 90 nm mini@sic:  22,5 keuro/block (65 nm) against 18,6 keuro/block

(3) the results of simulation using the new "variable resolution" feature are very encouraging and push us to an early production of a small chip

(4) we missed in any case the opportunity to produce a first prototype @90 nm this year, because of its large cost increase between June and September run

We propose to move directly to a 65 nm prototype. This is a preliminary schedule to produce new LAMBs for 2013:

(1) Mini@sic submission:   	spring or october 2011.
(2) delivery:			~february 2012
(3) tested 			~June 2012
(4) MPW submission:		from June 2012    (here last week we have put October 2012, but German people could work on MPW while we work on mini@sic).
(5) Delivery:			from November 2012
(6) Tested:			from February 2013
(7) MPW Production 		from February 2013
(8) Delivery 			from July 2013
(9) mounted on new Lambs	from autumn 2013

Power for the mini@sic TSMC 65 nm:

I/O = 2,5 V
core = 1,2 Volts.

Could be our final choice also for the MPW, even if MPW has a wider range of possibilities?

Agenda:

(0) Paola Giannetti   - 30 minutes - Overview about the mini@sic designs - plans for the future - costs - schedule.

(1) Francesco Crescioli - Standard Cell design - details  {block diagrams, routing, critical lines...}  20 minutes

(2) Matteo Beretta - Full custum design  -  20 minutes  [Matteo puoi trovare qui http://www.pi.infn.it/~paola/FTK/tesi_v4.pdf utlimo cap. belle figure]

(3) Ilaria Sacco -  20 minutes - Simulation and test vectors.

(4) Alberto Annovi -  30 minutes  - Changes to be implemented into our 2D chip. Variable resolution patterns ....

(5) Paola + discussion - 30 minutes - EU applications and other funding staff. - Possible collaboration 

(5)