Seventh INFN International School on: "Architectures, tools and methodologies for developing efficient large scale scientific computing applications" ESC15 - Bertinoro (Forlì-Cesena) Italy 25-31 October 2015

from to (Europe/Rome)
at Bertinoro
Material
Go to day
  • Sunday, 25 October 2015
    • 17:00 - 20:30 Registration and Welcome
    • 20:30 - 22:00 Welcome Dinner
  • Monday, 26 October 2015
    • 09:00 - 18:30 Session 1
      • 09:00 Welcome and introduction 30'
        Speaker: Mauro Morandin (INFN - Padova)
        Material: Slides pdf file}
      • 09:30 Computer Architecture evolution and the performance challenge 1h0'
        Speaker: Vincenzo Innocente (CERN)
        Material: Slides pdf file}
      • 10:30 Coffee break 30'
      • 11:00 Computer Architecture evolution and the performance challenge 45'
        Speaker: Vincenzo Innocente (CERN)
      • 11:45 Hands-on environment checkout 45'
        Speakers: Dr. Francesco Giacomini (CNAF), Giulio Eulisse (CERN)
        Material: github exercise site link}
      • 12:30 Lunch break 1h30'
      • 14:00 Efficient C++ coding 45'
        Speaker: Dr. Francesco Giacomini (CNAF)
        Material: Slides pdf file}
      • 14:45 Efficiency C++ coding 45'
        Speaker: Dr. Francesco Giacomini (CNAF)
      • 15:30 Coffee break 30'
      • 16:00 C++ Hands-on 45'
        Speaker: Dr. Francesco Giacomini (CNAF)
      • 16:45 Consolidation 30'
      • 17:15 Students lightning presentations 45'
        Material: Slides pdf file}
    • 20:30 - 20:30 Dinner
  • Tuesday, 27 October 2015
    • 08:30 - 18:30 Session 2
      • 08:30 Efficient C++ coding 45'
        Speaker: Dr. Francesco Giacomini (CNAF)
      • 09:15 Efficient C++ coding 45'
        Speaker: Dr. Francesco Giacomini (CNAF)
      • 10:00 Coffee break 30'
      • 10:30 Efficient Memory management 45'
        Speaker: Giulio Eulisse (CERN)
        Material: Slides pdf file}
      • 11:15 Efficient Memory management 45'
        Speaker: Giulio Eulisse (CERN)
      • 12:00 Consolidation 1h30'
      • 13:30 Lunch break 1h30'
      • 15:00 Introduction to parallel computing (basic concepts) 45'
        Speaker: Dr. Tim Mattson (Intel)
        Material: Slides pdf file}
      • 15:45 Introduction to parallel computing with OpenMP 45'
        Speaker: Dr. Tim Mattson (Intel)
        Material: Slides pdf file}
      • 16:30 Coffee break 30'
      • 17:00 Parallel Performance concepts using OpenMP 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 17:45 Students lightning presentations 45'
        Material: Slides pdf file}
    • 20:30 - 20:30 Dinner
  • Wednesday, 28 October 2015
    • 08:30 - 19:30 Session 3
      • 08:30 Efficient Memory management 45'
        Speaker: Giulio Eulisse (CERN)
      • 09:15 Efficient Memory management 45'
        Speaker: Giulio Eulisse (CERN)
      • 10:00 Coffee break 30'
      • 10:30 A "Hands-on" introduction to OpenMP 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 11:15 A "Hands-on" introduction to OpenMP 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 12:00 Consolidation 1h30'
      • 13:30 Lunch break 1h30'
      • 15:00 Working with OpenMP: Performance Optimization 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 15:45 Working with OpenMP: Debugging Applications 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 16:30 Coffee break 30'
      • 17:00 Consolidation 1h30'
      • 18:30 Evening Lecture: "Are we going back to the RISC era?" 1h0'
        The computer industry typically moves forwards in spirals with hardware or software moving from being deprecated (and even being laughed at) to being the hottest feature imaginable. Think of virtualization as an example. It existed on IBM mainframes already more than 30 years ago.
        The speaker will debate whether the "world" is interested in spiralling back to multivendor hardware solutions like we had in the 90s with multiple RISC-vendors competing ferociously in the desktop/server space.
        Although the speaker has been involved in the field for more than 40 years he will give no guarantees as to predicting the future!
        
        
        Speaker: Mr. Sverre Jarp (CERN)
        Material: Slides pdf file}
    • 20:00 - 22:30 Social dinner
      Bistrot Restaurant (Bertinoro)
  • Thursday, 29 October 2015
    • 08:30 - 19:00 Session 4
      • 08:30 Floating point computing efficiency 45'
        Speaker: Vincenzo Innocente (CERN)
        Material: Slides pdf file}
      • 09:15 Floating point computing efficiency 45'
        Speaker: Vincenzo Innocente (CERN)
        Material: exercises link}
      • 10:00 Coffee break 30'
      • 10:30 Vectorization 45'
        Speaker: Vincenzo Innocente (CERN)
        Material: exercises link}
      • 11:15 GPUs and the Heterogeneous programming problem 45'
        Speaker: Dr. Tim Mattson (Intel)
        Material: Slides pdf file}
      • 12:00 Consolidation 1h30'
      • 13:30 Lunch 1h30'
      • 15:00 GPU programming with OpenCL: Core Ideas and the host program 45'
        Speaker: Dr. Tim Mattson (Intel)
        Material: Slides pdf file}
      • 15:45 Consolidation 1h30'
      • 17:15 Coffee break 30'
      • 17:45 Consolidation 15'
      • 18:00 Evening lecture: "Low-power computing with System-on-Chips" 1h0'
        The embedded and high-performance computing sectors have in the past been very isolated and unaware of each other’s needs and technologies. Similar isolations have occurred between HPC and the mobile/tablets commodity markets.  We are now experiencing a very important convergence between markets, both in constraints and needs as well as in technologies. High computational demands, power consumption limitation, parallelism, heterogeneous computing and cost effectiveness are now driving constraints of both the HPC and embedded sectors. This convergence opens the way to the possibility of performing scientific computation on low power architecture originally developed for the embedded or mobile world. In this talk, we present the panorama of the low power architectures suitable for scientific computation. The INFN experience in building a low power cluster based on System-on-Chips (SoCs) is discussed together with the performance results in terms of power ratio and energy consumption obtained on that cluster. The applications used in the tests range from synthetic benchmarks to real life use cases. Results are compared to those obtained on traditional HPC architectures. An overview of the current European projects on low power computing for exascale HPC machine is finally presented. 
        Speaker: Daniele Cesini (CNAF)
        Material: Slides pdf file}
    • 20:00 - 20:00 Dinner
  • Friday, 30 October 2015
    • 08:30 - 22:00 Session 5
      • 08:30 Programming GPUs with OpenCL: Kernel programs 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 09:15 Programming GPUs with OpenCL: Performance issues 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 10:00 Coffee break 30'
      • 10:30 Lecture 45'
      • 11:15 Cluster Computing with MPI 45'
        Speaker: Dr. Tim Mattson (Intel)
        Material: Slides pdf file}
      • 12:00 Consolidation 1h30'
      • 13:30 Lunch 1h30'
      • 15:00 The 10 core constructs every MPI programmer should know 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 15:45 Geometric decomposition and MPI 45'
        Speaker: Dr. Tim Mattson (Intel)
      • 16:30 Coffee break 30'
      • 17:00 Information 5'
        Speaker: Mauro Morandin (PD)
        Material: Slides pdf file}
      • 17:05 Consolidation 1h30'
      • 18:35 Big Data: What happens when data actually gets big? 1h0'
        There are Big Data problems today. Usually when researchers talk about Big Data, however, the data isn't that big. An inefficient solution stack based on direct products over data-sets (Map-Reduce/Hadoop), cramming data (the square peg) into whatever data-store is available (the round hole), and moving data around between data-severs and
        computer-servers: all of this is OK if Big Data is not that big. But what happens when the data in Big Data actually gets big?
        In this talk we will discuss how Big Data software solution stacks must evolve to address future Big Data problems. Our guiding principles are that in a world where Big Data is really big:
        * One size does not fit all; data must match the data store
        * Data movement is everything; move queries and processing to the data
        * Visualization must be a first class citizen of the Big Data solution stack
        We are developing a reference implementation of the sort of Big Data solution stack we envision will play a key role in the future. We call this the BigDAWG solution stack. The research behind BigDAWG is occurring within the Intel Science and Technology Research Center at MIT with collaborators from Brown University, University of Washington, University of Tennessee, and Portland State University.
        Speaker: Dr. Tim Mattson (Intel)
        Material: Slides pdf file}
      • 20:00 Social dinner 2h0' ( Locanda della Fortuna )
    • 20:30 - 20:30 Dinner
  • Saturday, 31 October 2015
    • 08:30 - 14:50 Session 9
      • 08:30 Students feedback 30'
      • 09:00 Final examination 2h0'
      • 11:00 Coffee break 30'
      • 11:30 Delivery of certificates of attendance 30'
      • 12:00 Lunch 1h15'
      • 13:30 Shuttle departure (to Forli' railway station) 20'