IAPP school: VHDL design

Europe/Rome
250 (INFN-Pisa)

250

INFN-Pisa

Edificio C - Largo Bruno Pontecorvo 3, Pisa
    • 09:00 09:30
      Field Programmable Gate Arrays (FPGA) 30m
      Slides
    • 09:30 10:30
      Introduction to VHDL for FPGAs: some examples of simple logic 1h
      Slides
    • 10:30 12:30
      Exercise: 2h
      write code for a 16 bit register - check syntax - synthesis write code for a MUX: from two 16 bits inputs to one 16 bit but output - check syntax - synthesis write code for a 8 bit counter - check syntax - synthesis write code for a comparator - check syntax - synthesis If time in addition: write top level putting together the MUX, the regs, the comparator as shown in the figure - check syntax - synthesis
    • 12:30 14:30
      Lunch time 2h
    • 14:30 15:00
      How to perform behavioural simulation 30m
      Slides
    • 15:00 17:00
      exercise: use of the ISE simulation 2h
      simulate and check the VHDL code written in the morning
    • 09:30 10:00
      VHDL: Finite State Machines 30m
      Slides
    • 10:00 10:30
      What does our specific FSM 30m
      Slides
    • 10:30 12:30
      Exercise 2h
      - write code of the FSM that can handle the flux of data of the attached figure - check syntax - synthesis
    • 12:30 14:30
      Lunch time 2h
    • 14:30 15:00
      the test bench 30m
      Slides
    • 15:00 17:00
      Exercise 2h
      - Create a test bench for the flux of data and the FSM. - Simulate simple events flowing in the system.
    • 09:30 10:00
      FPGA Implementation 30m
      Slides
    • 10:00 10:30
      FIFO and RAM from Core Generator to the VHDL code 30m
      Slides
    • 10:30 12:30
      Exercise: add the Input Fifos and the Spy buffer to the project 2h
      - generate the FIFO and RAM modules - insert them in the top level and connect them to rest of the logic - synthesis - reports - behavioral simulation
    • 12:30 14:30
      Lunch 2h
    • 14:30 14:50
      Implementation 20m
      - brief description of Map, Place & root - options - simulation after implementation
    • 14:50 15:05
      brief introduction to other ISE tools - one example of design Floorplanning 15m
      - Constraint Editor - PlanAhead - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - Timing Analyzer - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - FPGA Editor - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - XPower Analyzer - just mentioned (no time to use it) - you can exercise by yourself after 17 pm - iMpact - will be used in the Lab session
      document
      Slides
    • 15:05 17:05
      Exercise: implementation and post-imp simulation 2h
      - implement the project with defaults - simulation post implementation - analysis of reports, in particular timing results - use of the constraint editor, put the output registers in the pads - if time is enough, look the project with PlanAhead
    • 09:30 10:00
      Chipscope and debugging 30m
      Slides
    • 10:00 10:30
      Isertion of chipscope in the project - 30m
    • 10:30 11:00
      CAEN demonstration: introduction about the boards 30m
    • 11:00 12:30
      Hands on in the LAB 1h 30m
    • 12:30 14:30
      Lunch 2h
    • 14:30 16:30
      Lab Session 2h
      - simple CAEN demonstration - programming chips in the FTK crate - Logic running in the FTK crate - chipscope use -oscilloscope use
      Slides