Top_Count Project Status (10/21/2015 - 17:42:04)
Project File: contatore_editt.xise Parser Errors:
Module Name: Top_Count Implementation State: Synthesized
Target Device: xc3s700an-4fgg484
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
1 Warning (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 27 5888 0%
Number of Slice Flip Flops 54 11776 0%
Number of 4 input LUTs 51 11776 0%
Number of bonded IOBs 17 372 4%
Number of GCLKs 2 24 8%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Oct 21 17:42:02 201501 Warning (0 new)1 Info (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/21/2015 - 17:42:05