Top_Count Project Status (10/21/2015 - 17:42:04) | |||
Project File: | contatore_editt.xise | Parser Errors: | |
Module Name: | Top_Count | Implementation State: | Synthesized |
Target Device: | xc3s700an-4fgg484 |
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No Errors |
Product Version: | ISE 14.7 |
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1 Warning (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slices | 27 | 5888 | 0% | |
Number of Slice Flip Flops | 54 | 11776 | 0% | |
Number of 4 input LUTs | 51 | 11776 | 0% | |
Number of bonded IOBs | 17 | 372 | 4% | |
Number of GCLKs | 2 | 24 | 8% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Oct 21 17:42:02 2015 | 0 | 1 Warning (0 new) | 1 Info (0 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |